Embedded microprocessor based systems typically include a number of components including: a microprocessor for executing instructions; read-only memory (ROM) for storing instructions; random-access memory (RAM) for storing instructions and data; as well as an interface to various input/output (I/O) devices such as a display, keyboard, serial connector, Ethernet, etc. An example of such an embedded system is shown in FIG. 1 to which attention is now directed.
FIG. 1 contains a block diagram 100 illustrating a processing element 102 coupled to a memory management unit (MMU) 104. The memory management unit 104 is coupled to a cache 106 which is coupled to a memory 108. In operation, the processing element 102 presents an address for instructions (or data) that is to be read from the memory 108 to the cache 106. If the cache 106 contains the instructions/data at the presented address, the instructions/data are provided to the processing element 102 without interfacing to the memory 108. However, if the cache. 106 does not contain the instructions/data at the presented address, the address is provided to the memory 108 for retrieval of the instructions/data. One skilled in the art will appreciate that the MMU 104 translates a virtual address provided by the processing element 102 into a physical address for the cache 106 (for a physically tagged cache) and for the memory 108.
More complex systems often contain multiple microprocessors (e.g., digital signal processors, graphics processors, etc.), each with their own memory systems, and often of different architecture (i.e., executing different instruction sets). Referring to FIG. 2 a block diagram 200 is shown having N number of processing elements 202, 204 and 206, each with their own memory system 208, 210, and 212, respectively. Early multiprocessor systems, such as is shown in FIG. 2, were implemented using different chips, mounted on a printed circuit board, and interconnected with signal lines on the printed circuit board. However, modern implementations are moving towards providing an entire system on a chip (SoC), as designated by dashed line 201. That is, a design engineer utilizes existing processing cores (elements), and existing memory structures to design multiprocessor SoC's for particular applications. Such SoC's allow for miniaturization of multiprocessing systems, and thus provide a lower cost alternative to the multi-chip, printed circuit board designs.
As shown in FIG. 2, when a SoC design requires multiple processing elements, of the same or different architecture, existing designs have chosen to support such processing elements by providing separate memory systems, and I/O device maps for each processing element. But, as the number of processing elements increases, so has the number of independent memory systems. However, the proliferation of independent memory systems is probably not the most economical solution. Multiple, large memory systems being accessed in parallel consume undesirable amounts of current. In addition, when providing independent memory systems for each processing element, the amount of memory that must be provided is the sum of the maximum runtime needs of each processing element. Memory in SoC's takes up considerable space oh the chips, and thus adds to the cost of manufacture, as well as runtime cost of the chips.
Therefore, what is needed is a memory management system for SoC's that allows a unified memory system to be utilized by multiple processing elements using a virtual memory system.